This invention relates to a semiconductor device having at least one high-voltage transistor whose output circuit is applied with higher voltage than the power supply voltage.
This invention also relates to a semiconductor device which is a heating resistance drive IC for heat-sensitive paper, a liquid crystal drive IC or the like having multiple high-voltage transistors whose output circuits are applied with higher voltage than the power supply voltage.
This invention also relates to a structure for a MOS transistor and a semiconductor integrated circuit device including the MOS transistor, more particularly to a structure for electrically isolating a MOS transistor.
This invention also relates to a semifinished silicon wafer product comprising extremely fine chips which is usable for production of document reading ICs for use in fax machines and thermal transfer ICs.
FIG. 2 shows the electrical circuit of a prior-art thermal head driver IC for passing a current of about 10 Ma through resistances for heating heat-sensitive paper. Multiple output pads 11 are provided along the edge of the semiconductor device chip. The pads are connected with drive transistor TD1-TDN. The gates of the transistors TD1-TDN are applied with voltage by a driver control circuit 12. The driver control circuit 12 operates at the power supply voltage. The heat-sensitive paper resistances are connected in series with the pads. A high voltage (about 35 V) is applied to the heat-sensitive paper resistances. When a transistor turns ON, a current of 10 mxc3x85 passes through the associated resistance and the heat-sensitive paper is discolored by the Joule heat of the resistance.
In the prior-art semiconductor device with CMOS circuitry, the low-voltage MOSFETs used in the driver control circuit are constituted as protective transistors for preventing breakdown of the output circuit by static electricity from the pad terminals. An N+-type source region and drain region are formed on the surface of a P-type silicon substrate and the gate is formed on a gate oxide film on the semiconductor substrate surface between the source region and the drain region. The drain region is electrically connected to the pad terminal by a wire. The source region and gate are electrically connected to the Vss terminal of the power supply by a wire. When static electricity appears on a pad terminal, breakdown of the internal semiconductor elements is prevented by discharging it through this protective transistor.
In the heat-sensitive paper type printer, for example, high-voltage MOS transistors of the structure shown in FIG. 3 are used as the drive transistors of the thermal head IC for driving the heating resistances. Specifically, an N+-type source region 4 and drain region 5 are formed on the surface of a single-crystal P-type silicon substrate 1. To obtain a high-withstand-voltage characteristic, a low-concentration drain region 21 is formed under a field insulating film 7 to be in contact with the drain region 5. The channel-forming region is the surface of the substrate 1 between the source region 4 and the drain region 21. The impedance of the channel-forming region is controlled by a gate 8 formed on the substrate 1 via a gate insulating film 6.
In the case of an IC for driving heating resistances, the drain withstand voltage is 30-50 V. The gate insulating film 6 is therefore formed as a silicon oxide film having a thickness of 500-1500 xc3x85. The assignee earlier developed and applied for patent on an IC with a thin gate insulating film (see Japanese Patent Application Public Disclosure No. Hei 7-226505).
When the drive control circuit uses CMOS construction, the transistors of one conductivity type are formed in well regions constituting deep diffused regions. In this case, the wells are separated by long distances to electrically isolate them from each other. FIG. 4 is a sectional view showing the structure used for well isolation in the ordinary prior-art semiconductor integrated circuit device. Nwells 101, 102 are formed in the vicinity of the surface of a P-type semiconductor substrate 100 at a spacing of about 8 xcexcm and a LOCOS 103 is formed between the Nwells 101, 102 to electrically isolate them from each other. In addition, each of the Nwells 101 and 102 is formed near the surface thereof with a MOS transistor consisting of a P+-type drain 104, source 105 and polyslicon gate 106. The P-type semiconductor substrate 100 has a resistivity of 20-30 xcexa9.cm and an Nwell ion implantation concentration of 4xc3x971012/cm2, and is thermally diffused at 1150xc2x0 C., 6H.
In the prior-art semiconductor device, however, the electrostatic withstand voltage decreases with decreasing transistor size.
Moreover, the prior-art semiconductor device having protective transistors cannot be applied to a semiconductor device whose output circuit operates at a voltage above 20 V because the drain withstand voltage of the protective transistors is below 20 V. In addition, attempts to increase the withstand voltage have complicated the fabrication process.
In the prior-art high-voltage MOS transistor, the shallow diffusion depth of the low-concentration drain region for obtaining the high-voltage characteristic has high resistance so that the area of the transistor has to be made large for enabling passage of a large current. An attempt to overcome this problem by increasing the concentration of the drain region 21 so as to lower its resistance causes the drain withstand voltage to fall below 10 V. If an attempt is made to solve it by increasing the diffusion depth while maintaining the low-concentration, the drain region 21 also becomes large in the lateral direction, resulting in a large transistor.
On the other hand, the MOS transistor with the Nwell drain structure used to obtain a high withstand voltage involves an Nwell isolation technology problem. The problem is that, owing to the long the lateral diffusion length of the Nwells, the distance between adjacent Nwells has to be at least twice the diffusion length. Moreover, since the impurity concentration of the P-type regions between adjacent Nwells is low, the depletion layer spreads widely during low voltage application, so that the Nwell spacing has to be at least twice the width of the depletion layer during application of the power supply voltage.
In addition, the semiconductor device integrating high-voltage MOS transistors and low-voltage MOS transistors requires a photolithographic step for forming the low-concentration drain regions of the high-voltage MOS transistors. In other words, one more photolithographic step is required than in the case of integrating only ordinary low-voltage MOS transistors.
The difficulty of reducing cost has also been a problem when very thin ICs are aligned in an IC module, since the nature of the application makes it impossible to shorten the IC length. If the IC width is reduced, there is a problem that a nondefective product may be marked as a defective one owing to the large size of the bad mark and the low positioning accuracy. Furthermore, since ICs are ordinarily flat, it has not been possible to package them in a cylindrical IC module.
It is an object of the present invention to provide a semiconductor device which eliminates the aforesaid shortcomings of the prior art and a method of fabricating the semiconductor device.
Another object of the invention is to provide a semiconductor device which exhibits an excellent electrostatic withstand voltage even when its transistors are reduced in size.
Another object of the invention is to provide a semiconductor device requiring application of a high pad terminal voltage of not less than 20 V, which owing to provision of easily producible protective transistors is high in reliability and low in cost.
Another object of the invention is to provide an IC module for overcoming problems of the prior art, which is low in production cost and also usable as a nonplanar module.
Another object of the invention is to provide a semiconductor device enabling a large current to be passed through a small area in a high-voltage MOS transistor whose drain region is applied with a high voltage of not less than 10 V.
Another object of the invention is to provide a method of simply and inexpensively fabricating a semiconductor device which is an integrated circuit comprising at least one high-drain-withstand-voltage MOS transistor whose drain region is applied with a high voltage of not legs than 10 V and at least one low-drain-withstand-voltage MOS transistor whose drain region is applied with a low voltage of not greater than 5 V.
The invention semiconductor device for achieving these objects is characterized as follows:
(1) A semiconductor device comprising a substrate of a first conductivity type, multiple output pad terminals arranged linearly on the surface of the substrate, high-voltage drive transistor and electrostatic protection transistor pairs connected in series between the output pad terminals and a power supply line, and a drive control circuit for controlling gates of the high-voltage drive transistors.
(2) The semiconductor device of (1), wherein the high-voltage drive transistors and the electrostatic protection transistors are MOSFET transistors and the channel length of the electrostatic protection transistors and is shorter than the channel length of the high-voltage drive transistors.
(3) The semiconductor device of (1), wherein the drain withstand voltage of the electrostatic protection transistors is lower than the drain withstand voltage of the high-voltage drive transistors.
(4) A semiconductor device comprising an electrostatic protection transistor having a drain region electrically connected with an output pad terminal, a source region electrically connected with a power source line, and a gate electrically connected with the power source line, the drain region being constituted of a low-concentration drain region of a second conductivity type formed on the surface of a semiconductor region of a first conductivity type and a high-concentration drain region formed on a surface within the low-concentration drain region, and the gate being formed on a field insulating film formed on the semiconductor region between the source region and the low-concentration drain region.
(5) The semiconductor device of (4), wherein a field doped region of a first conductivity type having a higher concentration than the semiconductor region is formed on the surface of the semiconductor region between the source region and the low-concentration drain region.
(6) The semiconductor device of (4), wherein the source region includes a high-concentration source region and a low-concentration source region symmetrical with the drain regions.
(7) The semiconductor device of (4), further comprising a MOSFET transistor of the second conductivity type formed on the surface of the semiconductor region, a well of the second conductivity type formed on the surface of the semiconductor region and a MOSFET transistor of the first conductivity type formed on the surface of the well, the low-concentration drain region and the well having the same impurity distribution.
(8) A semiconductor device comprising a source region of a second conductivity type formed on the surface of a semiconductor substrate of a first conductivity type, a first drain region of the second conductivity type formed on the surface of the semiconductor substrate to be separated from the source region by a channel-forming region, a second drain region of the second conductivity type formed on the surface of the semiconductor substrate in contact with the first drain region, a gate formed on the channel-forming region via a gate insulating film, and a punch-through prevention region of the second conductivity type formed on the surface of the semiconductor substrate where the channel-forming region and the first drain region are in contact, the first drain region being formed to a deeper diffusion depth and lower surface concentration than the second drain region and the punch-through prevention region being formed to a deeper diffusion depth than the second drain region.
(9) The semiconductor device of (8), further comprising a field insulating film of greater thickness than the gate insulating film formed between an end portion of the gate and the first drain region.
(10) The semiconductor device of (8), wherein the punch-through prevention region and the second drain region are formed in self-alignment with the field insulating film.
(11) The semiconductor device of (8), further comprising a second source region of the same impurity distribution as the first drain region formed between the source region and the channel-forming region.
(12) A semiconductor device comprising a first diffused region of a first conductivity type formed over a whole surface of a semiconductor substrate of a first conductivity type to have a higher concentration than the substrate and second and third diffused regions of a second conductivity type formed an the surface of the substrate to a depth of not less than 1.5 xcexcm at locations separated by 1.5-3.0 xcexcm to have a higher concentration than the first diffused region.
(13) The semiconductor device of (12), further comprising field-effect transistors respectively utilizing first and second insulating films and respectively formed on surfaces of the second and third diffused regions.
(14) The semiconductor device of (13), wherein the first diffused region is formed to a depth between the depth of the source and drain regions of the field-effect transistors utilizing the first and second insulating films and the depth of the second and third diffused regions.
(15) A semiconductor device comprising a source region of a second conductivity type formed on the surface of a semiconductor region of a first conductivity type, a first drain region of the second conductivity type formed on the surface of the semiconductor region to be separated from the source region by a channel-forming region, a second drain region of the second conductivity type formed on the surface of the semiconductor region in contact with the first drain region, a gate formed on the channel-forming region via a gate insulating film and the first drain region via a field insulating film, and an impurity region containing more first conductivity type impurity element than the semiconductor region formed on the surface of the first drain region.
(16) A semiconductor device comprising a low-drain-withstand-voltage MOSFET transistor of a second conductivity type formed on the surface of a semiconductor region of a first conductivity type and a high-drain-withstand-voltage MOSFET transistor formed on the surface of the semiconductor region to be separated from the low-drain-withstand-voltage MOSFET transistor by an isolation region, the isolation region including a field doped region of a first conductivity type formed on the surface of the semiconductor region to have a higher concentration than the semiconductor region and a field insulating film formed on the field doped region, and a drain region of the high-drain-withstand-voltage MOSFET consisting of an impurity region of the second conductivity type including the field doped region and having a higher concentration than the field doped region.
The semiconductor device fabrication method for achieving the objects of the invention is characterized as follows:
(17) A method of fabricating a semiconductor device including a low-drain-withstand-voltage MOSFET transistor of a second conductivity type formed on the surface of a semiconductor region of a first conductivity type and a high-drain-withstand-voltage MOSFET transistor formed on the surface of the semiconductor region to be separated from the low-drain-withstand-voltage MOSFET transistor by an isolation region, the method comprising the steps of forming an oxidation-resistant mask film on the surface of the semiconductor, selectively etching the oxidation-resistant mask film to remove portions thereof corresponding to the isolation region and a low-concentration drain region of the high-drain-withstand-voltage MOSFET transistor, implanting portions of the surface of the semiconductor region corresponding to the isolation region and the low-concentration drain region with impurity ions of the first conductivity type using the oxidation-resistant mask film as a mask, forming a resist film on the surface of the semiconductor region, removing portions of the resist film corresponding to the low-concentration drain region, implanting impurity ions of the second conductivity type using the resist film as a mask, forming a field oxide film by selective oxidation of the surface of, the semiconductor region using the oxidation-resistant mask film as a mask, the selective oxidation step forming a field doped region on the surface of the semiconductor region under the field oxide film of the isolation region, forming the low-concentration drain region and a field oxide film on the low-concentration drain region, removing the oxidation-resistant mask film and forming a gate insulating film on the surface of the semiconductor region, patterning gates of the low-drain-withstand-voltage MOSFET transistor and the high-drain-withstand-voltage MOSFET transistor on the gate insulating film, and forming source and drain regions of the low-drain-withstand-voltage MOSFET transistor and the high-drain-withstand-voltage MOSFET transistor by doping the surface of the semiconductor region with impurity of the second conductivity type using the gates as a mask.
Other features characterizing the invention are as follows:
(18) A semiconductor device comprising first source and drain regions of a first conductivity type formed on the surface of a semiconductor region of a second conductivity type, second drain and source regions of the first conductivity type formed on the surface of the semiconductor region to be separated from the first source and drain regions by an element isolation region of the second conductivity type, a field insulating film formed on the element isolation region of the second conductivity type, and an impurity region containing more first conductivity type impurity element than the semiconductor region formed on the surface of the element isolation region.
(19) A semiconductor device comprising a series connection of at least one MOS transistor and a diffused resistance which depletes at a voltage lower than the drain withstand voltage of the MOS transistor.
(20) The semiconductor device of (19), comprising a series connection of multiple MOS transistors whose drains are connected together and the diffused resistance.
(21) The semiconductor device (19), wherein at least part of the diffused resistance is of MOS structure.
(22) The semiconductor device (19), wherein the diffused resistance is formed in an isolation region of a MOS integrated circuit.
(23) A high-voltage MOSFET semiconductor device comprising a source region and a drain region of a second conductivity type formed apart from each other on the surface of a semiconductor region of a first conductivity type, a gate insulating film formed on a channel-forming region constituted by the surface of the semiconductor region between the source region and the drain region, and a gate formed on the gate insulating film, the drain region being constituted of a high-concentration drain region and a low-concentration drain region formed between the channel-forming region and the high-concentration drain region, and the voltage of the high-concentration drain region during weak inversion or inversion of the channel-forming region being set lower than the applied drain voltage.
(24) The high-voltage MOSFET semiconductor device of (23), wherein the channel-forming region between the source region and the low-concentration drain region has a channel length of not more than 2.5 xcexcm and the thickness of the gate insulating film is not more than 200 xc3x85.
(25) The high-voltage MOSFET semiconductor device of (23), further comprising a substrate electrode region of a first conductivity type formed on the surface of the semiconductor region apart from the source region.
(26) A semifinished silicon wafer product comprising a silicon wafer having a surface formed with multiple ICs marked off by a matrix of scribed lines, each IC consisting of multiple identical transistors arrayed linearly and the surface of at least one IC being marked with a bad mark of a diameter in the range of 100-200 xcexcm.
(27) A method of fabricating a semifinished silicon wafer product comprising the steps of forming multiple ICs marked off by a matrix of scribed lines on the surface of a silicon wafer, polishing the rear surface of the silicon wafer thereby reducing the thickness of the silicon wafer, conducting a probe test to measure electrical properties of the ICs and marking the surface of defective ICs with bad marks, the step of marking with bad marks being conducted by laser beam irradiation to control the diameter of the bad marks within the range of 100-200 xcexcm.
(28) The method of fabricating a semifinished silicon wafer product of (27), wherein the marking step comprises the steps of causing a YAG laser to emit a laser beam, leading the laser beam to near the silicon wafer by a fine optical fiber with a diameter of not more than 100 xcexcm, and focusing the laser beam from the optical fiber on the IC surface with an optical lens thereby forming a heat damaged region.
(29) A semiconductor integrated circuit comprising an HVMISFET (high-drain-withstand-voltage MOSFET) formed on a semiconductor region and having a gate insulating film of a thickness in the range of 100-200 xc3x85 and an LVMISFET (low-drain-withstand-voltage MOSFET) of the same conductivity type formed on the same semiconductor region and having the same threshold voltage and gate insulating film as the HVMISFET, the surface concentration of the semiconductor region directly under the gate insulating film being partially increased to make the threshold voltage not less than 0.7 V and drain regions and source regions of the HVMISFET and the LVMISFET being constituted as phosphorus impurity regions.
(30) The semiconductor integrated circuit of (29), wherein the minimum gate length in the channel length direction of the LVMISFET is in the range of 1.5-2.5 xcexcm.
(31) The semiconductor integrated circuit of (29), wherein the HVMISFET comprises a source region and drain region of a second conductivity type formed apart from each other on the surface of a semiconductor region of a first conductivity type, a channel-forming region which is the surface of the semiconductor region between the source region and the drain region, a gate formed on the channel-forming region via the gate insulating film, the drain region being constituted of a low-concentration drain region and a high-concentration drain region in contact with each other, the low-concentration drain region being disposed between the channel-forming region and the high-concentration drain region, and a field insulating film with a thickness at least one order of ten greater than that of the gate insulating film formed by self-alignment above the low-concentration drain region.
(32) A method of fabricating a semiconductor integrated circuit including an HVMISFET of a second conductivity type and an LVMISFET of the same conductivity type formed on a semiconductor region of first conductivity type, the method comprising the steps of forming an oxide mask film on the semiconductor region, removing regions of the oxide-mask film to become an isolation region and a low-concentration drain region of the HVMISFET by etching using a photosensitive film, implanting portions of the semiconductor region to become the low-concentration drain region with impurity ions of the second conductivity type using the oxide-mask film as a mask, forming a field oxide film by selective oxidation of the surface of the semiconductor region using the oxide-mask film as a mask, removing the oxide-mask film and forming a 100-200 xc3x85 insulating film on the semiconductor region to simultaneously form gate insulating films of the HVMISFET and the LVMISFET, implanting the surface of the semiconductor region under the gate insulating films of the HVMISFET and the LVMISFET with impurity ions of the first conductivity type for defining a threshold voltage using the field insulating film as a mask, patterning conductive films to become gates on the gate insulating films, and forming a high-concentration drain region of the HVMISFET, a source region of the HVMISFET, a drain region of the LVMISFET and a source region of the LVMISFET by implanting ions of the second conductivity type using the gates and the field insulating film as a mask.
Since the invention provides the electrostatic protection transistor in parallel with the drive transistor, static electricity appearing on the output pad is discharged through the protective transistor. As the drive transistor is therefore not required to discharge static electricity, it can be fabricated in a small size.
Since the invention achieves a high-voltage characteristic by constituting the drain region of a low concentration of 1016 atoms/cm3-1018 atoms/cm3 to a diffusion depth of not less than 1 xcexcm and forming a punch-through prevention region of the opposite conductivity type from the drain region in contact with the drain region, diffusion spread in the lateral direction is prevented to enable a small planar size. Since the spread of the diffusion in the depth direction is large compared with that in the lateral direction, the drain region has low concentration and high withstand voltage. Since it also has low resistance, it can pass a large current.
By using laser irradiation to form small bad marks, the invention enables production of a silicon wafer comprising extremely fine chips. Since the laser beam is transmitted to the silicon wafer through a fine optical fiber and focused on the chips by a condenser lens positioned near the silicon wafer, the laser beam can be condensed to a small spot that produces a small bad mark.
The semiconductor device according to the invention has the following features:
(1) Superior in electrostatic withstand voltage characteristic.
(2) Low in fabrication cost owing to the small size of the high-voltage drive transistor.
(3) Easy to fabricate.
The invention will be better understood and the other objects and advantages thereof will be more apparent from the following detailed description of preferred embodiments with reference to the accompanying drawings.